HDL Codes to realize Logic Gates

AIM:-To Design & Implement basic logic gates  using Verilog HDL.

Objective: The main objective of this program is to learn writing test bench and verify the functionality of the basic logic gates like AND, NAND, OR, NOR , XOR, XNOR,NOT etc., for an n-input gate and  simulate, synthesize and view RTL schematics for the same.

TOOL:-Xilinx ISE 9.2i Version

Logic gates symbola and description:

VERILOG SOURCE CODE: logic Gates

module logicgates1(a, b, c);
input a;
input b;
output
[6:0] c;
assign c[0]= a & b;
assign c[1]= a | b;
assign
c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a

End module

USER CONSTRAINTS FILE: 

#PACE: Start of Constraints generated by PACE 
#PACE: Start of PACE I/O Pin Assignments 
NET "a"  LOC = "p74"  ; 
NET "b"  LOC = "p76"  ; 
NET "c_and"  LOC = "p84"  ; 
NET "d_or"  LOC = "p85"  ; 
NET "e_not"  LOC = "p86"  ; 
NET "f_nand"  LOC = "p87"  ; 
NET "g_nor"  LOC = "p89"  ; 
NET "h_xor"  LOC = "p90"  ; 
NET "i_xnor"  LOC = "p92"  ; 
#PACE: Start of PACE Area Constraints 
#PACE: Start of PACE Prohibit Constraints 
#PACE: End of Constraints generated by PAC

Synthesis Report:

Simulation Results:

Viva Questions

1. What are different styles of programming in verilog?

2. What is simulation?

3. What is synthesis?

4. What tool you are using to implement different digital circuits?

5. What do you know about AC & DC analysis?

Outcomes of Experiment:

The outcome of this programme is students will learn how to write test bench, simulate and how to synthesize the circuit using Verilog language.