Design & Implement 4-BIT COMPARATOR program using Verilog HDL

AIM:-To Design & Implement 4-BIT COMPARATOR program using Verilog HDL.
Objectives: The main objective of this program is to learn how to use ternary operator using 3 conditions
TOOL:-Xilinx ISE 9.2i Version

ARCHITECTURE:

Truth Table

Source code:

module comp4bit(eq,gr,ls,a,b);
input [3:0] a,b;
output eq,gr,ls;
assign eq = (a==b) ? 1 : 0;
assign gr = (a>b) ? 1 : 0;
assign ls = (a<b) ? 1 : 0;
endmodule

Test Bench:

module comp4bittb();
reg [3:0] a,b;
wire eq,gr,ls;
comp4bit c1 (eq,gr,ls,a,b);
initial begin
a=4'b0000;b=4'b0000;
end
always #80 a[3]=~a[3];
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #80 b[0]=~b[0];
always #40 b[1]=~b[1];
always #20 b[2]=~b[2];
always #10 b[3]=~b[3];
initial #320 $stop;
endmodule

SIMULATED  WAVEFORMS:-

RTL SCHEMATIC:-

SYNTHESIS REPORT:-

TIMING REPORT:-

DEVICE UTILIZATION SUMMARY:-

SYNTHESIS DIAGRAM:-

CONCLUSION:-
The 4-bit comparator was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Viva Questions

1.      What is Verilog?
2.     What are the various modeling used in Verilog
3.      What is LUT.
4.     What are the differences between MUX and DMUX.
5.     What are the differences between a comparator and MUX.
6.     What is the top down modeling?
7.     What are the applications of the comparator?
8.     Why don’t we use just one NMOS or PMOS transistor as a transmission gate? 
9.     Why don’t we use just one NMOS or PMOS transistor as a transmission gate? 
10.     What are set up time & hold time constraints? What do they signify? 
11.     Explain Clock Skew?
12.     What is the structural gate-level modeling? 
13.     What is Switch-level modeling?
14.     What are identifiers?
15.     What is the structural Domain in Verilog

Outcomes: The main outcome of this program is to findout the largest/smallest/equal among two numbers using ternary operator.This statement is used generally to compare two numbers.