Design & Implement 4-BIT COUNTER  program using Verilog HDL

AIM:-To Design & Implement 4-BIT COUNTER  program using Verilog HDL.
Objectives: The main objective of this program is to write a code for counter and differentiate between Binary and BCD counters
TOOL:-Xilinx ISE 9.2i Version

ARCHITECTURE:-

TRUTH TABLE:-

SOURCE CODE:- Synchronous counter

module counter4bit(count,clk,clr);
input clk,clr;
output [3:0] count;
reg [3:0] count;
initial count = 4'b0000;
always @ (posedge clk)
begin
if(clr==1'b1)
count<=4'b0000;  
else
count <= count +1'b1;
end
endmodule

// For Asynchronous counter  give individual clocks 

TEST BENCH:-

module counter4bit(count,clk,clr);
input clk,clr;
output [3:0] count;
reg [3:0] count;
initial count = 4'b0000;
always @ (posedge clk)
begin
if(clr==1'b1)
count<=4'b0000;  
else
count <= count +1'b1;
end
endmodule

SIMULATED WAVEFORMS:-

RTL SCHEMATIC:-

SYNTHESIS REPORT:-

TIMING REPORT:-

DEVICE UTILIZATION SUMMARY:-

SYNTHESIS DIAGRAM:-

CONCLUSION:- The 4-bit counter was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.
Outcomes: Students must write the code on their own and dump into FPGA kit and verify the functionality.