Design & Implement 8X1 MULTIPLEXER program using Verilog HDL

AIM:-To Design & Implement 8X1 MULTIPLEXER program using Verilog HDL.
Objectives:  The main objective of this program is how to use small modules into a large module. 
                         the same 8x1 mux can be constructed using  ifelse statements and using 2x1 or 4x1 muxes.

TOOL:-Xilinx ISE 9.2i Version

Architecture:

Truth table:

SOURCE CODE:-

module mux(y,s,in);
output  y;
input [7:0] in;
input [2:0] s;
reg y;
always @(s)
begin
if(s==3'd0) y=in[0];
else if(s==3'd1) y=in[1];
else if(s==3'd2) y=in[2];
else if(s==3'd3) y=in[3];
else if(s==3'd4) y=in[4];
else if(s==3'd5) y=in[5];
else if(s==3'd6) y=in[6];
else  y=in[7];
end
endmodule

Test bench

module tb_mux();
reg [7:0]in;
reg [2:0]s;
wire y;
mux m1(y,s,in);
initial
begin
in=8'b10110110;
s[0]=1'b0;
s[1]=1'b0;
s[2]=1'b0;
end
always #40  s[2]=~s[2];
always #20  s[1]=~s[1];
always #10  s[0]=~s[0];
initial
begin
#200 $finish;
end
endmodule

SIMULATED WAVEFORMS:-

RTL SCHEMANTIC:-

SYNTHESIS REPORT:-

TIMING REPORT:-

DEVICE UTILIZATION SUMMARY:-

SYNTHESIS DIAGRAM:-

CONCLUSION:-
The 8X1 mux using 2X1 mux was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Viva Questions

    1. What are the advantages of Silicon-on-Insulator process?
    2. Define Short Channel devices?
    3. Define Threshold voltage in CMOS?
    4. What is Body effect?
    5. What are the applications of the multiplexer?
    6. Why the signals are delayed when they are propagated through gate?
    7. What do you mean by El-more delay?
    8. What is the importance of buffer insertion?
    9. What is the difference between MUX and encoder?

  10. What is the advantage of BICMOS process?
Outcomes: The outcome of the program is they will learn how to use submodules in main program using structural model.