Design & Implement JK-FLIP FLOP program using Verilog HDL
AIM:-To Design & Implement JK-FLIPFLOP program using Verilog HDL.
Objectives: The main objective of this program is students will learn the difference between Sequential and Combinational circuits and how to use Clock Signal.
TOOL:-Xilinx ISE 9.2i Version
FAMILY |
SPARTAN 3 |
Device |
XC3S400 |
Package |
PQ208 |
Speed |
-4/-5 |
Synthesis |
XST(VERILOG/VHDL) |
Simulator |
ISE Simulator |
Architecture:
Truth Table:
q |
j |
k |
Q(t+1) |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
SOURCE CODE:-
module jkff(q,j,k,clk,clr);
input j,k,clk,clr;
output q;
reg q;
always @ (posedge clk)
begin
if(clr==1'b1)
q<=1'b0;
else if (j==1'b0 & k==1'b0)
q<=q;
else if (j==1'b0 & k==1'b1)
q<=1'b0;
else if (j==1'b1 & k==1'b0)
q<=1'b1;
else if (j==1'b1 & k==1'b1)
q<=~q;
end
endmodule
TEST BENCH:-
module jkfftb_v;
reg j,k,clk,clr;
wire q;
jkff uut (.q(q),.j(j),.k(k),.clk(clk),.clr(clr));
initial begin
j = 0;k = 0;
clk = 1'b1;
clr = 1'b1;
#10 clr=1'b0;
end
always #5 clk=~clk;
always #20 j=~j;
always #10 k=~k;
initial #160 $stop;
endmodule
SIMULATED WAVEFORMS:-
RTL SCHEMATIC:-
SYNTHESIS REPORT:-
TIMING REPORT:-
DEVICE UTILIZATION SUMMARY:-
SYNTHESIS DIAGRAM:-
CONCLUSION:-
The JK-Flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.
Outcome: Implementation of Clock circuits using FPGA Spartan 3kit.
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UpdatedNov 28, 2021
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Views5,490
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