Design and implement the 8x1 MULTIPLEXER with 2x1 MULTIPLEXERs program using Verilog HDL
AIM: To design and implement the 8x1 MULTIPLEXER with 2x1 MULTIPLEXERs program using Verilog HDL.
Objectives: The main objective of this program is how to use small modules into a large module.
the same 8x1 mux can be constructed using ifelse statements and using 2x1 or 4x1 muxes.
TOOLS: Xilinx ISE 9.2i version.
Family |
Spartan 3 |
Device |
XC3S400 |
Package |
PQ208 |
Speed |
-4/-5 |
Synthesis |
XST(VHDL/Verilog) |
Simulator |
ISE Simulator |
Truth Table:
S3 | S2 | S1 | Y |
0 | 0 | 0 | I0 |
0 | 0 | 1 | I1 |
0 | 1 | 0 | I2 |
0 | 1 | 1 | I3 |
1 | 0 | 0 | I4 |
1 | 0 | 1 | I5 |
1 | 1 | 0 | I6 |
1 | 1 | 1 | I7 |
ARCHITECTURE:
SOURCE CODE:
module mux8to1by2t01(y, i, s);
output y;
input [7:0] i;
input [2:0] s; // mux2x1(y, s, a, b);
reg y;
wire w1,w2,w3,w4,w5,w6;
mux2x1 u1(w1, s[0], i[0], i[1]);
mux2x1 u2(w2, s[0], i[2], i[3]);
mux2x1 u3(w3, s[0], i[4], i[5]);
mux2x1 u4(w4, s[0], i[6], i[7]);
mux2x1 u5(w5, s[1], w1, w2);
mux2x1 u6(w6, s[1], w3, w4);
mux2x1 u7( y, s[2], w5, w6);
endmodule
TEST BENCH:
module mux8to1by2to1_tb_v;
reg [7:0] i;
reg [2:0] s;
wire y;
mux8to1by2t01 u1(y, i, s);
initial begin
i = 8'h56;
s = 0;
end
always #10 s[0]=~s[0];
always #20 s[1]=~s[1];
always #30 s[2]=~s[2];
endmodule
SYNTHESIS DIAGRAM:
SYNTHESIS REPORT:
TIMING REPORT:
SIMULATION WAVEFORM:
DEVICE UTILIZATION SUMMARY:
CONCLUSION: The design is implemented on Spartan 3 FPGA board with synthesis and simulation.
Outcomes: The outcome of the program is they will learn how to use submodules in main program using structural model.
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UpdatedNov 28, 2021
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