Design & Implement 8X3 ENCODER program using Verilog HDL

AIM:-To Design & Implement 8X3 ENCODER program using Verilog HDL.

Objective: The main objective of this program is to learn writing test bench and verify the functionality of 8x3 encoder for an 2ⁿ-input and an n output gate and must simulate, synthesize and view RTL schematics for the same.

TOOL:-Xilinx ISE 9.2i Version

Architecture:

Truth Table:

SOURCE CODE:-

module encoder83(o,a,en);
input [7:0] a;
input en;
output [2:0] o;
reg [2:0] o;
always @ (a,en)
begin
if(en==1'b1)
case(a)
8'b00000001 : o=3'b000;
8'b00000010 : o=3'b001;
8'b00000100 : o=3'b010;
8'b00001000 : o=3'b011;
8'b00010000 : o=3'b100;
8'b00100000 : o=3'b101;
8'b01000000 : o=3'b110;
8'b10000000 : o=3'b111;
endcase
else
o=3'bzzz;
end
endmodule

TEST BENCH:-

module encoder83tb;
reg [7:0] a;
reg en;
wire [2:0] o;
encoder83 e1 (o,a,en);
initial begin
a=8'b00000000;
en=1'b1;
#10 a=8'b00000001;
#10 a=8'b00000010;
#10 a=8'b00000100;
#10 a=8'b00001000;
#10 a=8'b00010000;
#10 a=8'b00100000;
#10 a=8'b01000000;
#10 a=8'b10000000;
end
always #90 en=~en;
initial #120 $stop;
endmodule

Simulated Waveform:

RTL Schematic

SYNTHESIS REPORT:-

TIMING REPORT:-

DEVICE UTILIZATION SUMMARY:-

SYNTHESIS DIAGRAM:-

CONCLUSION:-

The 8X3 encoder was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.
Viva Questions

    1. List the Different types of oxidation techniques?
    2. What is the advantage of CMOS technology?
    3. What are the different layers in MOS transistors?
    4. What is Enhancement mode transistor?
    5. List various packages available.
    6. What is the number of gates available in the FPGA in our lab?
    7. How programmable switch/ Junction box work?
    8. What is the difference between encoder and multiplexer?
    9. What is priority encoder?
    10. List out the advantages of encoder?

Outcomes of Experiment:  From this program   students will expose how  to use and where to use   case statement  and simulate , synthesize the same.