Design and Implementation of 3x8 Decoder

AIM:-To Design & Implement 3X8 DECODER program using Verilog HDL.

Objective: The main objective of this program is to learn how to use CASE statement writing test bench and verify the functionality of 3x8 decoder and must simulate, synthesize and view RTL schematics for the same.

TOOL:-Xilinx ISE 9.2i Version

ARCHITECTURE:-

Truth Table:

SOURCE CODE:-

module decoder38(o,a,en);
input [2:0]a;
input en;
output [7:0] o;
reg [7:0] o;
always @ (a,en)
begin
if(en==1'b1)
case(a)
3'b000 : o=8'b00000001;
3'b001 : o=8'b00000010;
3'b010 : o=8'b00000100;
3'b011 : o=8'b00001000;
3'b100 : o=8'b00010000;
3'b101 : o=8'b00100000;
3'b110 : o=8'b01000000;
3'b111 : o=8'b10000000;

endcase
else
o=8'b00000000;
end
endmodule

TESTBENCH:-

module decoder38tb();
reg [2:0] a;
reg en;
wire [7:0] o;
decoder38 d1 (o,a,en);
initial begin
a=3'b000;
en=1'b1;
end
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #80 en=~en;
initial #160 $stop;
endmodule

SIMULATED WAVEFORMS:-

RTL SCHEMANTIC:-

SYNTHESIS REPORT:-

TIMING REPORT:-

DEVICE UTILIZATION SUMMARY:-

SYNTHESIS DIAGRAM:-

CONCLUSION:-

The 3X8 Decoder was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Viva Questions

1. What are four generations of Integration Circuits?

2. Give the advantages of IC?

3. Give the variety of Integrated Circuits?

4. Give the basic process for IC fabrication?

5. What are the various Silicon wafer Preparation?

6. List the libraries used in verilog.

7. What do you mean by RTL view.

8. What do you mean by synthesizable code.

9. State the difference between FPGA and CPLD.

10. What do you mean by CLB in FPGA.

Outcomes of Experiment: From this program students will expose how to use and where to use case statement