Design & Implement PRIORITY ENCODER program using Verilog HDL

AIM:-To Design & Implement PRIORITY ENCODER program using Verilog HDL.
Objectives:  The main objective of this program is how to use an enable input and differentiate between with and without priority logic using IF ELSE statement 
TOOL:-Xilinx ISE 9.2i Version

Architecture:

Truth Table:

SOURCE CODE:-

Module priorityenc (o,v,a,en);
input [7:0] a;
input en;
output v;
output [2:0] o;
reg [2:0] o;
assign v=|a;
always @ (a,en)
begin
if(en==1'b1)
begin
if(a[7]) o=3'b111;
else if(a[6]) o=3'b110;
else if(a[5]) o=3'b101;
else if(a[4]) o=3'b100;
else if(a[3]) o=3'b011;
else if(a[2]) o=3'b010;
else if(a[1]) o=3'b001;
else if(a[0]) o=3'b000;
else
o=3'bxxx;
end
else if(en==1'b0)
o=3'bzzz;
end
endmodule

TEST BENCH:-

module priorityenctb();
reg [7:0] a;
reg en;
wire v;
wire [2:0] o;
priorityenc p1 (o,v,a,en);
initial begin
a=8'b00000000;
en=1'b0;
end
always #1280 a[7]=~a[7];
always #640 a[6]=~a[6];
always #320 a[5]=~a[5];
always #160 a[4]=~a[4];
always #80 a[3]=~a[3];
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #2 en=1'b1;
always #2560 $stop;
endmodule

SIMULATED WAVEFORMS:-

RTL SCHEMATIC:-

SYNTHESIS REPORT:-

TIMING REPORT:-

SYNTHESIS DIAGRAM:-

CONCLUSION:-
The Priority encoder was designed using Verilog HDL & implanted in FPGA Spartan 3 kit.
Viva Questions
    1. What is Depletion mode Device?
    2. When the channel is said to be pinched –off?
    3. Give the different types of CMOS process?
    4. What are the steps involved in twin-tub process? 
    5. What are the advantages of priority encoder over encoder?
    6. What do you mean by speed specification in FPGA/CPLD?
    7. What do you mean by synthesis?
    8. How IO blocks are utilized in the FPGA.
    9. How to protect IO blocks from ESD.

  10. Draw the protection circuit.

Outcomes: The outcome of this program is to use IF ELSE statement and dump the program into FPGA SPARTAN kit.