Design and Implement MOORE MACHINE program using Verilog HDL
AIM:-To Design & Implement MOORE MACHINE program using Verilog HDL.
Objectives: The main objective of this program is to design state machines.
TOOL:-Xilinx ISE 9.2i Version
FAMILY | SPARTAN 3 |
---|---|
Device | XC3S400 |
Package | PQ208 |
Speed | -4/-5 |
Synthesis | XST( VERILOG/VHDL) |
Simulator | ISE Simulator |
Architecture:
Truth Table:
Present | state | Input | Next | state | Output |
A |
B |
x |
Ta(t+1) |
Tb(t+1) |
Y=AB |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
State Diagram:
Source Code:
module mooremachine2(y, x, clk, rst);
output y;
input x;
input clk;
input rst;
reg [1:0]state;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
always@(posedge clk or negedge rst)
if(~rst)
state=s0;
else
case(state)
s0:if(x)
state=s1;
else
state=s0;
s1:if(x)
state=s2;
else
state=s1;
s2:if(x)
state=s3;
else
state=s2;
s3:if(x)
state=s0;
else
state=s3;
endcase
assign y=state[0]&state[1];
endmodule
Test bench:
module tb_mooremachine2();
reg clk,rst,x;
wire y;
mooremachine2 m44(y,clk,rst,x);
initial
begin
clk=1'b0;
rst=1'b0;
x=1'b0;
end
always #10 clk=~clk;
always #20 x=~x;
always #200 rst=~rst;
initial
begin
#1000 $finish;
end
endmodule
Simulation waveform:
RTL SCHEMATIC:-
SYNTHESIS REPORT:-
TIMING REPORT:-
DEVICE UTILIZATION SUMMARY:-
SYNTHESIS DIAGRAM:-
CONCLUSION:-
The Moore machine was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.
Outcomes: The main outcome of this program is to write code for real time modules.
Viva Questions:
-
What is Moore machine?
-
What are the differences between Mealy and Moore machines?
-
Explain the advantages of the Moore machine?
-
What is the significance of state diagram?
-
What is the difference between excitation table and truth table?
-
What is the implication of imperfect clock signal?
-
What do you mean by clock jitter?
-
Name different hazards?
-
How to realize high speed digital circuits.
-
List various low power VLSI techniques?
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UpdatedNov 29, 2021
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