AIM:-To Design & Implement FULL-ADDER program using Verilog HDL.
Objectives: Students will  learn the various types of  programming models like Dataflow, Structural and Behavioural .
TOOL:-Xilinx ISE 9.2i Version

 FAMILY SPARTAN 3 Device XC3S400 Package PQ208 Speed -4/-5 Synthesis XST(VERILOG/VHDL) Simulator ISE Simulator

Architecture: Truth Table:

A

B

C_in

C_out

SUM

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

SOURCE CODE:-
Dataflow Modeling:

``````module fulladddataflow(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign#2 p=a&b;
assign#2 q=b&c;
assign#2 r=c&a;
assign#4 sum=a^b^c;
assign#4carry =(p1 | p2) | p3;``````

Behavioral Modeling:

``````module fuladbehavioral(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
reg sum,carry;
reg p1,p2,p3;
always @ (a or b or c) begin
sum = (a^b)^c;
p1=a & b;
p2=b & c;
p3=a & c;
carry=(p1 | p2) | p3;
end
endmodule``````

Structural Modeling:-

``````module fulladder(s,co,a,b,cin);
input a,b,cin;
output s,co;
wire t1,t2,t3;
xor x1 (t1,a,b);
xor x2 (s,t1,cin);
and x3 (t2,a,b);
and x4 (t3,t1,cin);
or x5 (co,t2,t3);
endmodule``````

Test Bench:

``````module fulladdertb();
reg a,b,cin;
wire s,co;
initial begin
{a,b,cin}=3'b000;
End
always #40 a=~a;
always #20 b=~b;
always #10 cin=~cin;
initial #80 \$stop;
endmodule``````

SIMULATED WAVEFORMS:- RTL SCHEMATIC:- SYNTHESIS REPORT:- TIMING REPORT:- DEVICE UTILIZATION SUMMARY:- SYNTHESIS DIAGRAM:- CONCLUSION:-
The Full adder was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Viva Questions
1. Why is NAND gate preferred over NOR gate for fabrication?

2. What is Body Effect?

3. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

4. What is the fundamental difference between a MOSFET and BJT?

5. What is the disadvantage with carry chain?

6. What is the purpose of guard rings?

7. List any two non-synthesizable verilog statements.

8. What is the difference between Spartan 3E and Vertex FPGA.

9. What is the number of NAND gates required to implement a 3-bit full adder?

10. What is the number of NOR gates required to implement a 3-bit full adder?

Outcomes: The outcome of this program is know the difference between the three modeling styles and when to use and where is it suitable.

• Updated
Nov 28, 2021
• Views
439
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