Design & Implement FULL-ADDER

AIM:-To Design & Implement FULL-ADDER program using Verilog HDL.
Objectives: Students will learn the various types of programming models like Dataflow, Structural and Behavioural .
TOOL:-Xilinx ISE 9.2i Version

FAMILY	SPARTAN 3
Device	XC3S400
Package	PQ208
Speed	-4/-5
Synthesis	XST(VERILOG/VHDL)
Simulator	ISE Simulator

Architecture:

Truth Table:

A	B	C_in	C_out	SUM
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

SOURCE CODE:-
Dataflow Modeling:

module fulladddataflow(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign#2 p=a&b;
assign#2 q=b&c;
assign#2 r=c&a;
assign#4 sum=a^b^c;
assign#4carry =(p1 | p2) | p3;

Behavioral Modeling:

module fuladbehavioral(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
reg sum,carry;
reg p1,p2,p3;
always @ (a or b or c) begin
sum = (a^b)^c;
p1=a & b;
p2=b & c;
p3=a & c;
carry=(p1 | p2) | p3;
end
endmodule

Structural Modeling:-

module fulladder(s,co,a,b,cin);
input a,b,cin;
output s,co;
wire t1,t2,t3;
xor x1 (t1,a,b);
xor x2 (s,t1,cin);
and x3 (t2,a,b);
and x4 (t3,t1,cin);
or x5 (co,t2,t3);
endmodule

Test Bench:

module fulladdertb();
reg a,b,cin;
wire s,co;
fulladder f1 (s,co,a,b,cin);
initial begin
{a,b,cin}=3'b000;
End
always #40 a=~a;
always #20 b=~b;
always #10 cin=~cin;
initial #80 $stop;
endmodule

SIMULATED WAVEFORMS:-