Design and implement BCD Counter using verilog HDL

Aim: To design and implement BCD Counter  using  verilog    HDL
Objective: Functionality of BCD counter and must able to develop the code 
Tools: Xilinx ISE 9.2i version

Family	Spartan 3
Device	XC3S400
Package	PQ208
Speed	-4/-5
Synthesis	XST
Simulator	ISE Simulator

 

Architecture:

Truth Table:

Clk	Clr	Q3	Q2	Q1	Q0
0	1	0	0	0	0
1	0	0	0	0	1
1	0	0	0	1	0
1	0	0	0	1	1
1	0	0	1	0	0
1	0	0	1	0	1
1	0	0	1	1	0
1	0	0	1	1	1
1	0	1	0	0	0
1	0	1	0	0	1
1	0	0	1	0	0
1	0	1	0	1	0
1	0	1	0	1	1
1	0	1	1	0	0
1	0	1	1	0	1
1	0	1	1	1	0
1	0	1	1	1	1

 

Source Code:

module bcd9(count,rst,clk);
input rst,clk;
output [3:0]count;
reg [3:0]count;
always @(posedge clk , negedge rst)
begin
if(~rst)
count=4'b0000;
else if(count<4'b1001)
count=count+4'b0001;end
endmodule

 

Test bench:

module tb_bcd9();
reg rst,clk;
wire [3:0]count;
bcd9 c1(count,rst,clk);
initial
begin
rst=1'b0;
clk=1'b0;end
always #10 clk=~clk;
always #300 rst=1'b1;
initial
begin
#1000 $finish;
end
endmodule

 

Simulation waveform:

Schematic Diagram:

Synthesis Report:

1. Timing Report:

Clock Information:

Clock Signal | Clock buffer(FF name) | Load |

clk | BUFGP | 4 |

Asynchronous Control Signals Information:

Control Signal | Buffer(FF name) | Load |

rst_inv(rst_inv1_INV_0:O) | NONE(count_3) | 4 |

 

Timing Summary:

Speed Grade: -4

Minimum period: 4.036ns (Maximum Frequency: 247.770MHz)

Minimum input arrival time before clock: No path found

Maximum output required time after clock: 7.367ns

Maximum combinational path delay: No path found

Timing Detail:

All values displayed in nanoseconds (ns)

========================================================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 4.036ns (frequency: 247.770MHz)

Total number of paths / destination ports: 26 / 8

-------------------------------------------------------------------------

Delay: 4.036ns (Levels of Logic = 1)

Source: count_3 (FF)

Destination: count_0 (FF)

Source Clock: clk rising

Destination Clock: clk rising

Data Path: count_3 to count_0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------------------------------------------ ------------

FDCE:C->Q 3 0.720 1.246 count_3 (count_3)

LUT4:I0->O 4 0.551 0.917 count_cmp_lt00001 (count_cmp_lt0000)

FDCE:CE 0.602 count_0

----------------------------------------

Total 4.036ns (1.873ns logic, 2.163ns route)

(46.4% logic, 53.6% route)

========================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 4 / 4

-------------------------------------------------------------------------

Offset: 7.367ns (Levels of Logic = 1)

Source: count_0 (FF)

Destination: count<0> (PAD)

Source Clock: clk rising

Data Path: count_0 to count<0>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDCE:C->Q 6 0.720 1.003 count_0 (count_0)

OBUF:I->O 5.644 count_0_OBUF (count<0>)

----------------------------------------

Total 7.367ns (6.364ns logic, 1.003ns route)

(86.4% logic, 13.6% route)

=========================================================

CPU : 7.98 / 8.29 s | Elapsed : 8.00 / 9.00 s

b) Device utilization Summary:

Selected Device : 3s50pq208-4

Number of Slices: 3 out of 768 0%

Number of Slice Flip Flops: 4 out of 1536 0%

Number of 4 input LUTs: 6 out of 1536 0%

Number of IOs: 6

Number of bonded IOBs: 6 out of 124 4%

Number of GCLKs: 1 out of 8 12%

b) Schematic Diagram:

Conclusion: The design is implemented on Spartan 3 FPGA board with Synthesis and Simulation.
Outcomes: Students will learn coding and dumping into FPGA KIT 

Viva Questions:
    1. What is Asynchronous counter?
    2. What is Johnson Counter?
    3. Give the Practical applications of counter?
    4. Draw the gate level circuit for 2-bit counter.
    5. What is ring counter?
    6. What is the purpose of preset and reset pins?
    7. What is the purpose of chip selection signal?
    8. What is the pin number of ground and VCC?
    9. What is the purpose of capacitor connected externally to IC?
    10. What is race around condition.