Design & Implement D-FLIPFLOP program using Verilog HDL.
AIM:-To Design & Implement D-FLIPFLOP program using Verilog HDL.
Objectives: The main objective of this program is students will learn the difference between Sequential and Combinational circuits and how to use Clock Signal.
TOOL:-Xilinx ISE 9.2i Version
FAMILY |
SPARTAN 3 |
Device |
XC3S400 |
Package |
PQ208 |
Speed |
-4/-5 |
Synthesis |
XST(VERILOG/VHDL) |
Simulator |
ISE Simulator |
Architecture:
Truth Table: (high=up arrow)
CLK |
D |
RST |
Q |
QBAR |
high |
1 |
0 |
1 |
0 |
high |
0 |
0 |
0 |
1 |
high |
1 |
0 |
1 |
0 |
high |
0 |
0 |
0 |
1 |
VERILOG SOURCE CODE:
Behavioral Modeling:
module srflipflop(s, r, clk, rst, q, qbar);
input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if(s==1'b0 && r==1'b0)
begin
q=q; qbar=qbar;
end
SOURCE CODE:-
module dff(q,qbar,clk,rst,d);
input d,clk,rst;
output q,qbar;
reg q,qbar;
always @ (posedge clk ,negedge rst)
begin
if(rst==1'b0)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=d;
qbar=~q;
end
end
endmodule
TEST BENCH:-
module dfftb_v;
reg clk,rst,d;
wire q,qbar;
dff uut (.q(q),.qbar(qbar),.clk(clk),.rst(rst), .d(d));
initial begin
clk = 0;
rst = 0;
d = 0;
#10 rst=1'b1;
end
always #10 clk=~clk;
always #20 d=~d;
endmodule
SIMULATED WAVEFORMS:-
RTL SCHEMATIC:-
SYNTHESIS REPORT:-
TIMING REPORT:-
DEVICE UTILIZATION SUMMARY:-
SYNTHESIS DIAGRAM:-
CONCLUSION:-
The D-flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.
Outcomes: Outcome of this program is to work on conditional statements in all modeling styles.
-
UpdatedNov 28, 2021
-
Views1,501
Design and implement the 8x1 MULTIPLEXER with 2x1 MULTIPLEXERs program using Verilog HDL
Design & Implement 8X1 MULTIPLEXER program using Verilog HDL
Design & Implement 4-BIT COMPARATOR program using Verilog HDL
Design & Implement JK-FLIP FLOP program using Verilog HDL
Design & Implement T-FLIPFLOP program using Verilog HDL
Design & Implement 4-BIT COUNTER program using Verilog HDL