Ddesign and implement the Demultiplexer using verilog HDL

Aim: To design and implement the Demultiplexer  using  verilog  HDL.
Objectives: The main objective of this program is to know the working of Demultiplexer and how to simulate and synthesize the same using always statement
Tools: Xilinx ISE 9.2i version

Architecture:

Truth Table:

SOURCE CODE:

module demux(y0,y1,y2,y3,y4,y5,y6,y7,s,in);
output y0,y1,y2,y3,y4,y5,y6,y7;
input [2:0]s;
input in;
reg y0,y1,y2,y3,y4,y5,y6,y7;
always @(s|in)
begin
case(s)
3'b000 : y0=in;
3'b001 : y1=in;
3'b010 : y2=in;
3'b011 : y3=in;
3'b100 : y4=in;
3'b101 : y5=in;
3'b110 : y6=in;
3'b111 : y7=in;
endcase
end
endmodule

Testbench:

module tb_demux();
reg [2:0]s;
reg in;
wire y0,y1,y2,y3,y4,y5,y6,y7;
demux d1(y0,y1,y2,y3,y4,y5,y6,y7,s,in);
initial
begin
in=1;
s=3'b000;
end
always #10 in=~in;
always #80 s[2]=~s[2];
always #40 s[1]=~s[1];
always #20 s[0]=~s[0];
initial
begin
#200 $finish;
end
endmodule

Simulation Waveform:

Schematic Diagram:

Synthesis Report:

Timing Report:

Timing constraint: Default OFFSET OUT AFTER for Clock 'y7_cmp_eq0000'

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------

Offset: 7.078ns (Levels of Logic = 1)

Source: y7 (LATCH)

Destination: y7 (PAD)

Source Clock: y7_cmp_eq0000 falling

Data Path: y7 to y7

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

LD:G->Q 1 0.633 0.801 y7 (y7_OBUF)

OBUF:I->O 5.644 y7_OBUF (y7)

----------------------------------------

Total 7.078ns (6.277ns logic, 0.801ns route)

(88.7% logic, 11.3% route)

================================================================

CPU : 7.76 / 8.07 s | Elapsed : 7.00 / 8.00 s

Device utilization summary:

Selected Device : 3s50pq208-4

Number of Slices: 4 out of 768 0%

Number of Slice Flip Flops: 8 out of 1536 0%

Number of 4 input LUTs: 8 out of 1536 0%

Number of IOs: 12

Number of bonded IOBs: 12 out of 124 9%

IOB Flip Flops: 8

Schematic Diagram After Synthesis:

Conclusion: The design is implemented on Spartan 3 FPGA board with Synthesis and Simulation.
Outcome:  The main outcome of this program is to students learn how to write the case statement using always and analysis of Delay, Area and Power will be  calculated.