Design of Full adder using 3 modeling styles
Prerequisites: Study the functionality of full adder circuit.
Learning Objective: To develop the source code for full adder by using VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA.
Software and Hardware: Xilinx ISE 9.2i and FPGA Spartan-3E.
Theory:
The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade for adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the previous full adder in the cascade. The carry output from the full adder is fed to next full adder in the cascade. The full adder is simply two half adders joined by an OR.
The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed this can be extended to a string of eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
The output carry is designated as Cin and the Sum output is designated as S. Take a look at the truth-table.
Block Diagrams:
Verilog Code:
(a) using Gate Level Modeling:
Simulation Results:
(b) Using Data Flow Modeling:
Simulation Results:
(c) Using Behavior Modeling:
Simulation Results:
Test Branch Code:
Result:
Designed Full adder using VERILOG code and simulated and synthesized using Xilinx tool.
Learning Outcome:
After completion of this experiment, students are able to design full adder using VERILOG code.
Viva Questions:
- What are the differences between half adder and full adder?
- What are the advantages of minimizing the logical expressions?
- What does a combinational circuit mean?
- Implement the half adder using Verilog HDL code?
- Implement the full adder using two half adders.
- What are the applications of adders?
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UpdatedOct 30, 2016
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