Design of 8-to-1 multiplexer

Prerequisites: Study of the functionality of multiplexers and de-multiplexer.

Learning Objective: To develop the source code for Multiplexer  by using VERILOG and obtain the simulation and synthesis.

Software and Hardware: Xilinx ISE 9.2i and FPGA Spartan-3E.

Theory:

In electronics, a multiplexer or mux is a device that selects one of several analog or digital input signals and forwards the selected input into a single line output. A multiplexer of 2ⁿ inputs has n select lines, which are used to select which input line to be sent to the output. An electronic multiplexer can be considered as a multiple-input, single-output switch i.e. digitally controlled multi-position switch. The digital code applied at the select inputs determines which data inputs will be switched to output.

 A common example of multiplexing or sharing occurs when several peripheral devices share a single transmission line or bus to communicate with computer. Each device in succession is allocated a brief time to send and receive data. At any given time, one and only one device is using the line. This is an example of time multiplexing since each device is given a specific time interval to use the line.

Table: Truth Table of 8:1 MUX

Figure: Logic Diagram of 8:1 MUX

Block Diagram:

Verilog Code:

Test Bench Code:

Simulation Results:

Result: Designed 8x1 multiplexer and verified by synthesizing and simulating the VERILOG code.

Learning outcome:

After completion of this experiment, students are able to design 8x1 multiplexer using Verilog.

Viva Questions:

1. What is meant by multiplexer?
2. What are the applications of multiplexer?
3. How many 8X1 multiplexers are needed to construct 64X1 multiplexer?
4. Compare multiplexer with encoder?
5. Design a full adder using 8X1 multiplexer?
6. In 2n to 1 multiplexer, how many selection lines are required?