Design of 4 bit Comparator

Prerequisites: Study of the functionality of Comparator.

Learning Objective: To develop the source code for 4 bit comparator by using VERILOG and obtained the simulation and synthesis.

Software and Hardware: Xilinx ISE 9.2i and FPGA Spartan-3E.

Theory:

The magnitude comparator can also be used to indicate equality. It has additionally two or more outputs, one that is logic 1 when word A is greater than word B, and another that is logic 1 when word A is less than word B. Magnitude comparators therefore form the basis of decision making in logic circuits. Any logical problem can be reduced to one or more (sometimes many) yes/no decisions based on a pair of compared values.

Input A=A3A2A1A0;

B=B3B2B1B0

Truth Table for 4 bit comparator

Block Diagram:

Verilog Code:

Test Bench Code:

Simulation Results:

Result:

Designed 4 bit comparator using Verilog code and  simulated and synthesized.

Learning outcome:

After completion of this experiment, students are able to design comparator using Verilog.

Viva Questions:

1. What does a digital comparator mean?

2. How many 4-bit comparators are needed to construct 12-bit comparator?

3. Design a 2-bit comparator using gates?

4. What are the applications of a comparator?

5. Derive the Boolean expressions of one bit comparator and two bit comparators.