The Cadence_Digital_labs directory contains Solutions folder and also Work folder. Inside Work folder you can make modifications of the code locally without affecting your Source code present inside Solutions directory. Lab directory details:
. /Solutions Contains a local copy of all the lab experiments including Testbences for simulating the codes.
. /Workarea It’s a place to run Simulation and Synthesis.
In this lab, you will simulate a design using the Incisive simulator. You will:
* Create the cds.lib and hdl.var files
* Compile, elaborate, and simulate the design and testbench
- Change directory to Cadence_Digital_labs/Workarea/Gates.
- You will need to copy each file present in Solutions folder to Workarea/Gates location by using the below mentioned command :
cp -rf ../../Solutions/Gates/* .
- Change directory to AND folder.
- View the Code of AND gate and also the testbench for the same.
- This procedure is same for all the other logic gates present inside Gates folder.
- Set Up the Design Environment
Using your favorite text editor, create the cds.lib file and make the following entries:
Define and_lib ./and.lib
Create the local library directory:
Create the hdl.var file and make the following entry:
Define WORK and_lib
- Compile the Source Descriptions
(i). Compile the transmission gate description with the -messages option:
ncvlog and.v –messages
(ii). Compile the testbench description with the -MESS option:
ncvlog and_test.v –MESS
(iii) Elaborate the testbench:
ncelab and_test -access +rwc
(iv) Simulate the design: with -gui option:
ncsim and_test –gui
- The -gui option opens the Console and Design Browser windows.
- Selcet the input and output ports as shown above and click (waveforms symbol) button to open up the waveform window.
- . Invoke RTL Compiler by typing %u2015rc -gui on your terminal window.
- Give the path of the library with respect to the directory you are in using the command:
“set_attribute lib_search_path ../library”
- Give the path of the RTL files with respect to the directory you are in using the below command:
“set_attribute hdl_search_path ../rtl”
- Read the library from the directory specified in giving the path for the library files in step 11 using the command:
“set_attribute library slow_normal.lib”
“slow_normal.lib” is the name of the library file in the directory library. There is another library there in that directory with name “slow_highvt.lib”. Any one of these two libraries could be used at a time.
- Read the RTL files from the directory specified in the path in step 12. The RTL files are in the directory name %u2015rtl:
- Now Elaborate the design using “elaborate” command.
- Synthesize the circuit using the command:
“synthesize -to_mapped -effort medium”.
- Timing could be check using “report timing”.
- Similarly for Gates “report gates”.
- Check area using “report area”.
- Check Power dissipation using “report power”.