JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY 
HYDERABAD 
II Year B.Tech. ECE. II-Sem L T/P/D C 
4 -/-/- 4 
DIGITAL DESIGN USING VERILOG HDL 

---

Course Objectives:

This course teahces:

• Desigining digital circuits, behaviour and RTL modelin of digital circuits usin verilog HDL, verifying these Models and synthesizing RTLmodels to standard cell libraries and FPGAs.
• Students ain practical experience by designing, modeling, implemeting and verfying several digital circuits.

This course aims to provide students with the understanding of the different technologies related to HDLs, construct, compile and execute Verilog HDL prorams usin provided software tools. Design diital components and circuits that are testable, reusable, and synthesizable.

UNIT - I:

IntroductiontoVerilLog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Function Verification, System Tasks, Programming LanguageInterface, Module, Simulation and Synthesis Tools

Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space, Characters, Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Operators.

UNIT - II:

Gate Level Modeling: Introduction, AND Gate Primitive, ModuleStructure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances ofPrimitives, Design of Flip-Flops with Gate Primitives, Delay, Strengths and Construction Resolution, Net Types, Design ofBasicCircuit.

Modeling at Dataflow Level: Introduction, Continuous Assignment Structure, Delays and Continuous Assignments,Assignment to Vector, Operators.

UNIT - III:

Behavioural Modeling: Introduction, Operations and Assignments,Functional Bifuracation, 'Intial' Construct, Assignments with Delays, 'Wait'Construct, MultipleAlwaysBlock, Designsat Behavioural Level, Blocking and Non-Blocking Assignments, The 'Case' Statement, Simulation Flow, 'If' an 'if-Else' Constructs, 'Assign- De-Assign' Constructs, 'Repeat' Construct, for loop, 'The Disable' Construct, 'While Loop', Forever Loop, Parallel Blocks, Force-Release, Construct, Event.

UNIT - IV:

Switch LevelModeling: BasicTransistor Switches, CMOS Switches, BiDirectional Gates, Time Delays with Switch Primitives, Instantiation with 'Strenths' and 'Delays' Strength Contention with Trireg Nets.

System Tasks, Functions and Compiler Directives: Parameters, Path Delays, Module Parameters. SystemTasks and Functions,File Based Tasks and Functions, Computer Directives, Hierarchical Access,User Defined Prinitives.

UNIT - V:

Sequential Circuit Desription: Sequential Models - Feedback Model, Capacitive Model, Implicit Model, Basic Memory Components, Functional Register, Static Machine Coding, Sequential Synthesis.

Components Test and Verification: Test Bench - Combinational Circuits Testing, Sequential Circuit Testing, Test Bench Techiniques,Desin Verification, Assetion Verification.

TEXT BOOKS:

1. T.R. Padmanabhan, B Bala Tripura Sundari, Design Through Verilog HDL, Wiley 2009.
2. Zainalabdien Navabi, Verliog Digital System Design,TMH, 2nd Edition.

REFERENCE BOOKS:

1. Fundamentals ofDigital Logic with Verilog Design - Stephen Brown,Zvonkoc Vranesic, TMH, 2nd Edition.
2. Advanced Digital Logic Design using Verilog, State Machines & Synthesis for FPGA - Sunggu Lee, Cengage Learning, 2012.
3. Verilog HDL - Samir Palnitkar, 2nd Edition, Pearson Education, 2009.
4. Advanced Digital Design with Verilog HDL - Michel D. Ciletti, PHI,2009.

Course Outcomes:

By the end of this course, students should be able to:

• Describe Verilo hardware description, languages(HDL).
• Design digital circuits.
• Write Behavioural models of digital circuits.
• Write Register Transfer Level (RTL) models of Digital Circuits.
• Verify Behavioural and RTL models.
• Describe standard cell libraries and FPGAs
• Synthesize RTL models to standard cell libraries and FPGAs
• Implement RTL models on FPGAs and Testin and Verification