R09 - December, 2011 - Regular Examinations - Set - 4.
B.Tech II Year - I Semester Examinations, December 2011
ELECTRONIC DEVICES AND CIRCUITS
(COMMON TO EEE, ECE, CSE, EIE, BME, IT, MCT, E.COMP.E, ETM, ICE)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---
1.a) Explain Avalanche and Zener break down mechanisms in semiconductors and compare them?
b) For the Zener diode circuit shown in Figure.1, determine VL, VR , IZ & R. [5 10]
Figure.1
2.a) With reference to the Rectifiers, Explain the following terms:
i) Ripple Factor
ii) Efficiency
iii) Peak Inverse Voltage (PIV)
iv) % Regulation
b) A 230 V, 60Hz voltage is applied to the primary of a 5:1 step down, center tapped transformer used in a full wave rectifier having a load of 900?. If the diode resistance and the secondary coil resistance together have a resistance of 100 ?, determine i) DC voltage across the load.
ii) DC current flowing through the load.
iii) DC power delivered to the load.
iv) PIV across each diode. [8 7]
3.a) Draw the circuit diagram of NPN transistor in Common Collector (CC) configuration. With neat sketches and necessary equations, describe its static input- output characteristics and clearly indicate the cut-off, saturation & active regions on the output characteristics?
b) Derive the relationship among ?, ? and ? in transistors? [9 6]
4.a) What do you mean by biasing a transistor? Explain the need of biasing a transistor for the construction of a faithful amplifier?
b) Design an Emitter bias circuit using silicon transistor to achieve a stability factor of 20, with the following specifications: VCC = 16V, VBE = 0.7V, VCEQ = 8V,
ICQ = 4 mA & ?= 50. [7 8]
5.a) Draw the circuit and small-signal model of CE amplifier with unbypassed emitter resistor. Derive the expressions for input resistance & voltage gain?
b) A bipolar junction transistor with hie = 1100?, hfe = 50, hre = 2.4x10-4, hoe = 25 ?A/V, is to drive a load of 1K? in CB amplifier arrangement. Estimate AV, AI, Ri & R0. [8 7]
6.a) Explain the construction & operation of a N-channel MOSFET in enhancement and depletion modes with the help of static drain characteristics and transfer characteristics?
b) In an n-channel FET, the effective channel width is 3x 10-4cm and the donor impurity concentration is 1015 electrons/cm3. Find the pinch-off voltage? [10 5]
7.a) Show the self-bias arrangement for a Field Effect Transistor. With necessary expressions describe the procedure of Q-point establishment and stabilization?
b) In the common source FET amplifier shown in Figure.2, the transconductance and drain dynamic resistance of the FET are 5mA/V and 1M? respectively. Estimate AV, Ri & R0. [8 7]
Figure.2
8.a) With neat energy band diagrams, explain the V-I characteristics of Tunnel diode. Also discuss the negative resistance property of tunnel diode.
b) Draw the two-transistor model of SCR and explain its operation. [10 5]
********
ELECTRONIC DEVICES AND CIRCUITS
(COMMON TO EEE, ECE, CSE, EIE, BME, IT, MCT, E.COMP.E, ETM, ICE)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---
1.a) Explain Avalanche and Zener break down mechanisms in semiconductors and compare them?
b) For the Zener diode circuit shown in Figure.1, determine VL, VR , IZ & R. [5 10]
Figure.1
2.a) With reference to the Rectifiers, Explain the following terms:
i) Ripple Factor
ii) Efficiency
iii) Peak Inverse Voltage (PIV)
iv) % Regulation
b) A 230 V, 60Hz voltage is applied to the primary of a 5:1 step down, center tapped transformer used in a full wave rectifier having a load of 900?. If the diode resistance and the secondary coil resistance together have a resistance of 100 ?, determine i) DC voltage across the load.
ii) DC current flowing through the load.
iii) DC power delivered to the load.
iv) PIV across each diode. [8 7]
3.a) Draw the circuit diagram of NPN transistor in Common Collector (CC) configuration. With neat sketches and necessary equations, describe its static input- output characteristics and clearly indicate the cut-off, saturation & active regions on the output characteristics?
b) Derive the relationship among ?, ? and ? in transistors? [9 6]
4.a) What do you mean by biasing a transistor? Explain the need of biasing a transistor for the construction of a faithful amplifier?
b) Design an Emitter bias circuit using silicon transistor to achieve a stability factor of 20, with the following specifications: VCC = 16V, VBE = 0.7V, VCEQ = 8V,
ICQ = 4 mA & ?= 50. [7 8]
5.a) Draw the circuit and small-signal model of CE amplifier with unbypassed emitter resistor. Derive the expressions for input resistance & voltage gain?
b) A bipolar junction transistor with hie = 1100?, hfe = 50, hre = 2.4x10-4, hoe = 25 ?A/V, is to drive a load of 1K? in CB amplifier arrangement. Estimate AV, AI, Ri & R0. [8 7]
6.a) Explain the construction & operation of a N-channel MOSFET in enhancement and depletion modes with the help of static drain characteristics and transfer characteristics?
b) In an n-channel FET, the effective channel width is 3x 10-4cm and the donor impurity concentration is 1015 electrons/cm3. Find the pinch-off voltage? [10 5]
7.a) Show the self-bias arrangement for a Field Effect Transistor. With necessary expressions describe the procedure of Q-point establishment and stabilization?
b) In the common source FET amplifier shown in Figure.2, the transconductance and drain dynamic resistance of the FET are 5mA/V and 1M? respectively. Estimate AV, Ri & R0. [8 7]
Figure.2
8.a) With neat energy band diagrams, explain the V-I characteristics of Tunnel diode. Also discuss the negative resistance property of tunnel diode.
b) Draw the two-transistor model of SCR and explain its operation. [10 5]
********
-
CreatedSep 29, 2012
-
UpdatedSep 29, 2012
-
Views2,071