R09 - December, 2011 - Regular Examinations - Set - 4.

B.Tech II Year - I Semester Examinations, December2011

DIGITAL LOGIC DESIGN

(COMPUTER SCIENCE AND ENGINEERING)

Time: 3 hours Max. Marks: 75

Answer any five questions

All questions carry equal marks

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1. Perform the following subtraction in binary andcheck by converting the numbers to

decimal and subtracting.

a) 111.11 –101.1

b) 1101.1 -1010.01 [15]

2. Convert the following expressions to sum of theproduct form

a)(a’ b c)(a b’ c’)(abc)

b) (a b c’)(a’ b’ c’) (a’ b c) [15]

3. For the following expression using only NAND gates,design a combinational network.

abcd a’bc’d’ a’bc’d a’bcd’ don’t cares (a’b’c’d’ a’b’cd) [15]

4. Explain the Analysis and design procedure for a combinationalcircuit. Also design a binary multiplier. [15]

5. Explain the state reduction and state assignment in designingsequential circuit. Consider one example in the above process. [15]

6. Design a modulo 16 counter. [15]

7. Design a Random Access memory having 8 K Bytes. Identify how manyaddress lines are needed and also word length. [15]

8. Find the circuit that has no static hazards and implement theBoolean function for the following

F(A,B,C,D)= (0,2,6,7,8,10,12) [15]

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