VLSI Design Mid - II, November - 2014

1.Which of the following allows a larger no. of array elements to be utilized than a channeled array for the same size of die?
  • sea of gate arrays
  • channel gate array
  • structured gate array
  • none of the above
Answer: A
2.An embedded gate array or structured gate array is a combination of
  • CBIC
  • MGA
  • both A and B
  • none
Answer: C
3.Process of converting unoptimized Boolean description to a PLA format is known as
  • translation
  • flattening
  • mapping
  • factoring
Answer: B
4.Which of the following is not related in implementation of a logic/binary cell for storing one-bit
  • 2 inputs and 1 output
  • data input
  • select input enables the cell for reading and writing.
  • read/write input determines the cell operation when it is selected.
Answer: A
5.Which of the following is a volatile type of memory
  • DRAM
  • SRAM
  • Flash
  • none
Answer: B
6.Which of the following are process technologies in CPLD
  • EPROM, EEPROM and FLASH
  • SRAM, ANTIFUSE & EEPROM
  • FLASH, SRAM and ANTIFUSE
  • FLASH, SRAM & ANTIFUSE
Answer: A
7.In commercial FPGS chips, Look Up Tables usually have either 4 or 5 inputs which require _________ storage cells.
  • 16 and 24
  • 16 and 32
  • 8 and 16
  • 12 and 24
Answer: B
8.____ is the process of adding intermediate terms to add structure to a description.
  • translation
  • flattening
  • mapping
  • factoring
Answer: D
9.__________ is used for specified geometric design, interrelationships of mask
  • SRC
  • DRC
  • BRC
  • none
Answer: B
10.________ technology requires select transistor and storage transistor in each cell.
  • FLASH
  • SRAM
  • ANTIFUSE
  • EEPROM
Answer: D
11.The ___________ breaks the carry computation in to two steps starting with the computation of two intermediate values.
Answer: Carry-look ahead adder
12.___________ is the process of optimizing Boolean equation at the logic level and mapping them to a techno-specific library of cells.
Answer: Logic synthesis
13.__________ is the process of splitting a single design among multiple devices.
Answer: System partitioning
14.A __________ is tested by shifting a special pattern through the scan path before stuck at faults begins.
Answer: Scan path
15._________ provides each wire a route through a set of areas and avoids wasting of chip area
Answer: Global routing
16.JTAG stands for ____________________
Answer: Joint Test Acton Group
17.__________ are used to control the output of the optimization and mapping process.
Answer: Constraints
18.__________ is a degree to which it can be observed that node at output operates correctly.
Answer: Observability
19._____________ provides fixed interconnection of along with its four sides.
Answer: Switchbox routing
20.Fault coverage is defined as the percentage of fault that can be detected by the applied _________
Answer: Test vector