VLSI Design Mid - I, September - 2014
1.In the p-well process of CMOS fabrication ___________ substrate is used.
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P-type
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N-type
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C-type
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none
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Answer: A
2.Main drawback of BICMOS technology
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Low speed
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Higher power dissipation
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High cost
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High speed
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Answer: C
3.Steps involved in manufacturing of IC
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Oxidation
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Photolithography
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Ion implantation
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all
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Answer: D
4.________ is ideally suited for applications using battery power or battery backup power.
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MOS
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P-MOS
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N-MOS
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CMOS
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Answer: A
5.Identify different CMOS technologies
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N-well process
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P-well process
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Twin-tub process
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all
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Answer: D
6.VLSI means
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a device containing transistors between 103 and 105
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a device containing transistors between 105 and 107
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a device containing transistors between 103 and 104
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a device containing transistors between 105 and 109
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Answer: B
7.Latch up problems occurs in CMOS circuits due to
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Parasitic capacitance
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Parasitic bipolar transistors
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Parasitic resistance
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none
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Answer: B
8.Switching behaviour of MOS Transistor is characterized by __________
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Threshold voltage
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Doping
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Drain voltage
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Substrate
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Answer: A
9.Which of the following statements is incorrect?
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CMOS circuitry is more difficult to fabricate than NMOS or PMOS as it required devices of both polarities.
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CMOS gates have very good noise immunity that is typically 10% of the supply voltage.
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When a CMOS gate is static it has negligible power consumption.
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CMOS gates have logic levels close to the supply rails
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Answer: B
10.The ________ has a physical channel between the drain and source.
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D-MOSFET
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E-MOSFET
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V-MOSFET
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None
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Answer: A
11.The five basic chemical reactions pyrolosis, photolysis,reduction, oxidation or reduction-oxidation can be used in __________________
Answer: Chemical vapour deposition
12.Material used for metallization is _________________
Answer: Silver
13.Material used for gate oxide in MOS technology is _______________
Answer: SiO2
14.Impurity used in diffusion _______________
Answer: B2O3
15.In p-well CMOS fabrication ______________ well is formed.
Answer: P-well
16.Based on ______________ law number of transistors doubles for every 18 months.
Answer: Moore’s law
17.CMOS transistor is combination of ____________________ transistors.
Answer: N-MOS, P-MOS
18.Input impedance of MOS Transistor _________________ compared to BJT.
Answer: HIGH
19.Steps involved in twin tub process ________________
Answer: Tub Formation, Thin-oxide Construction, Source & Drain Implantation
20.__________________ are different types of MOSFET.
Answer: Enhancement type, depletion type