Switching Theory and Logic Design Mid - II, April - 2012
1.The ROM programmed during manufacturing process itself is called
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MROM
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PROM
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EPROM
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EEPROM
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Answer: A
2.A memory in which the contents get erased when power failure occurs is
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EAROM
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PROM
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ROM
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RAM
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Answer: D
3.A single literal term in SOP expression
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Requires an inverter for PLA implementation
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Requires an AND gate for PLA implementation
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Doesn't requires an AND gate for PLA implementation
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Doesn't requires an inverter for PLA implementation
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Answer: B
4.When an inverter is placed between the inputs of an S-R flip flop,the resulting flip flop is a
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J-K flip flop
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Master-Slave flip flop
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T flip flop
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D flip flop
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Answer: D
5.Flip flops can be used to make
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Latches
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Bounce - elimination switches
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Registers
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All the above.
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Answer: C
6.The output of a clocked sequential circuit is independent of the input.The circuit can be represented by
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Mealy model
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Moore model
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Either Mealy or Moore model
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Neither Mealy or Moore model
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Answer: B
7.For designing a finite state machine K-maps can be used for minimizing the
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Excitation expression of flip flops
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Number of flip flops
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Output logic expression
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Excitation and output logic expressions
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Answer: D
8.While constructing a state diagram of sequential circuit from the set of given statements
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A minimum number of states must only be used
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Redundant states may be used
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Redundant states must be avoided
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None of the above
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Answer: B
9.An ASM chart consists of
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Only state boxes
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Only decision boxes
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Only decision and conditional output boxes
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All the above
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Answer: D
10.Moore type outputs are
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Independent of the inputs
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Dependent only on the inputs
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Dependent on present state and inputs
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Any one of the above
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Answer: B
11.In a positive unite function all the variables are only in _____________ form.
Answer: Uncomplemented
12.______________ functions cannot be realized using a single threshold gate.
Answer: Unthreshold
13.Master -slave configuration is used in J-K flip flop to eliminate______________
Answer: Race around condition
14.A ___________ ring counter requires no decoding circuitry.
Answer: Basic
15.The process of assigning the states of a physical device to the states of a sequential machine is known as_______________.
Answer: State assignment
16.The merger table method of state reduction is also called ____________ method or ____________ method.
Answer: Paull, Implicant chart
17.A table which consists of the states of a minimal state machine is called a ________________
Answer: Implicant chart
18.The data processing path commonly referred as the _________ paths
Answer: Data
19.______ type of outputs are referred to as unconditional outputs.
Answer: Moore
20.A path through an ASM block from entry to exit is referred to as a _____________.
Answer: Link path