Embedded and Real Time Systems Mid - I, September - 2014
1._______ let’s designer specify functionality in an abstract manner and automatically generates low level implementation details
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Design technology
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Compilation
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PLD Technology
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IC Technology
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Answer: B
2.____________provide a software environment for the application of numerous tools throughout the design process and management of versions of implementation
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Compilation
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Verification
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Framework
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State machine
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Answer: C
3.____________ is feasible for applications such as disk drives ,printers ,scanners
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USB
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Fire wire
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IEEE483
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IEEE485
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Answer: B
4.The __________________stores and manipulates a system’s data
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FSM
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Controller
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Data path
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Manipulator
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Answer: C
5.An a ____________ architecture, the data & program words share the same memory space.
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Princeton
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Superscalar
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Harvard
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None
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Answer: A
6.___________ is a standard for interconnecting consumer electronic devices using serial bus
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IEEE484
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IEEE1394
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USB
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IEEE432
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Answer: B
7._______ is the task of reading the instruction from memory into instruction register.
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Decode
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Fetch instruction
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Store result
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Execute
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Answer: B
8.USB 2.0 standard supports data rates up to ________ Mbps.
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1.5 Mbps
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12Mbps
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480Mbps
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none of the above
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Answer: C
9.In Moore machine out put depends only on
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Present state
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previous state
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both
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none of the above
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Answer: A
10.The Embedded software is also called _______________
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Fire wall
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Firmware
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Fire wire
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none of the above
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Answer: B
11.USART is stands for ________________________
Answer: Universal Synchronous Asynchronous Receiver Transmitter
12.The mneumonic ASIC stands for _____________
Answer: Application Specific Integrated Circuit
13.A ___________ microprocessor which can execute two or more scalar operation in parallel requiring two or more ALU’s
Answer: Superscalar
14.The RT – level combinational component used to convert the binary input into n bit output is_________________
Answer: Decoder
15. ______________is a digital circuit whose outputs are a function of the present as well as previous input values.
Answer: Sequential circuit
16.We can merge a number of states into a single state reducing the size of the ______________.
Answer: Controller
17.The narrowest line that we can create on a chip is called the feature ______________.
Answer: Size
18._____________is the manner in which we convert our concept of desired system functionality into an implementation.
Answer: Design technology
19.___________tools are used to automate both the combinational and the sequential logic design.
Answer: CAD
20.____________monitors external control inputs as well as data path control outputs.
Answer: Controller