Computer Organization Mid - II, April - 2012

1.The command that causes the interface to respond by transferring data from the bus into one of its registers is____________
  • control command
  • status command
  • data output command
  • data input command
Answer: C
2.In polling, the drawback is___________
  • cost is more
  • complex hardware is required
  • time consuming
  • maintenance is more
Answer: C
3.The inter process communication mechanism used in tightly coupled system is___________
  • shared memory
  • FIFO
  • pipes
  • message queues
Answer: C
4.The IEEE 796 standard bus has _______ data _______address and________ control lines.
  • 36,24,36
  • 10,24,30
  • 16,24,26
  • 16,20,20
Answer: C
5.The RISC consists of only_______________ length instruction format.
  • variable
  • fixed
  • small number
  • large number
Answer: B
6.The function of the master control unit in SIMD processor is to ___________the instruction.
  • fetch
  • decode
  • execute
  • store
Answer: B
7.In the Memory Hierarchy, the following Memory has maximum access time
  • register
  • primary memory
  • cache
  • Magnetic tape
Answer: D
8.Boot strap loader requires_____________
  • RAM
  • ROM
  • Any Memory
  • Only Processor
Answer: B
9.If only cache location is updated during write operation as long as there is no replacement, the type of the cache memory is called_____________
  • write back
  • write both
  • write through
  • write once
Answer: A
10.Replacing the page that entered the memory at first is____________
  • FIFO
  • LRU
  • MRU
  • LFU
Answer: A
11.The time taken to access a particular sector is______________
Answer: latency time
12.A __________________ pipeline divides an arithmetic operation into sub operations for execution in the pipeline segments.
Answer: arthimetic
13.To protect data from being changed simultaneously by 2 or more processors is called _____________-
Answer: mutual exclusion
14.The technique of segmentation suffers which fragmentation ______________________
Answer: external
15.__________________ is a circuit that detects instructions whose source operands are destinations of instructions further up in the pipeline
Answer: interlocks
16.An array processor consists of _____________ instructions and _________________data organisation.
Answer: single, multiple
17.In four-way Set-Associative mapping, the number of tags are______________
Answer: four
18.In ___________________ bus, each data item is transferred during a time slice known to source and destination in advance.
Answer: synchronous
19.The transfer of data between main memory and cache is_______________
Answer: block
20.A faster and smaller memory in between cpu and main memory is ______________
Answer: cache memory