Computer Organization and Architecture Mid - II, April - 2012

1.One type of parallel processing that does not fit flynn’s classification is ________________ processing.
  • array
  • vector
  • multi port
  • pipeline
Answer: D
2.Multiprocessors are classified as multiple processor _________________systems.
  • MISD
  • SIMD
  • SISD
  • MIMD
Answer: D
3._______________ multiprocessor system consists of a number of processors connected through a common path to a memory unit.
  • common bus
  • cross bar
  • multi port
  • hypercube
Answer: A
4.The IEEE 796 standard bus has ____________ data _____________address and__________ control lines.
  • 36,24,36
  • 10,24,30
  • 16,24,26
  • 16,20,20
Answer: C
5.In _____________ mechanism only the cache is updated and location is marked so that it can be copied later into main memory.
  • write back
  • write both
  • write through
  • write once
Answer: A
6.In the memory hierarchy, the following memory has least capacity___________
  • register
  • primary memory
  • cache
  • Magnetic tape
Answer: A
7.Replacing the block that has been not used for the longest period of time is ______________
  • FIFO
  • LRU
  • MRU
  • LFU
Answer: B
8.In the following, which is efficient____________
  • Programmed i/o
  • Interrupt initiated i/o
  • Direct memory access
  • Memory mapped i/o
Answer: C
9.In polling, the drawback is_________________
  • cost is more
  • complex hardware is required
  • Time consuming
  • Maintenance is more
Answer: C
10.The number of basic I/O commands in IBM 370 computer IOP is _________________.
  • 50
  • 6
  • 8
  • 40
Answer: A
11.A __________________ pipeline divides an arithmetic operation into sub operations for execution in the pipeline segments.
Answer: Arithmetic
12.____________________ must be performed to resolve multiple contention for the shared resources.
Answer: arbitration
13.To protect data from being changed simultaneously by 2 or more processors is called _____________-
Answer: mutual exclusion
14.The bus controller that monitors the cache coherence problem is referred as _________________
Answer: snoopy cache controller
15.___________________ processing deals with computations involving large matrices.
Answer: vector
16.The Dynamic RAM consists of _________________.
Answer: capacitors
17.The transfer of data between main memory and cache memory is __________________
Answer: block
18.The technique of segmentation suffers which fragmentation ______________________
Answer: external
19.The time taken to access a particular sector is _______________
Answer: latency time
20.The circuit which provides the interface between computer and similar interactive terminal is ________
Answer: UART