Computer Organization and Architecture Mid - II, April - 2012
1.One type of parallel processing that does not fit flynn’s classification is ________________ processing.
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array
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vector
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multi port
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pipeline
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Answer: D
2.Multiprocessors are classified as multiple processor _________________systems.
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MISD
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SIMD
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SISD
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MIMD
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Answer: D
3._______________ multiprocessor system consists of a number of processors connected through a common path to a memory unit.
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common bus
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cross bar
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multi port
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hypercube
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Answer: A
4.The IEEE 796 standard bus has ____________ data _____________address and__________ control lines.
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36,24,36
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10,24,30
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16,24,26
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16,20,20
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Answer: C
5.In _____________ mechanism only the cache is updated and location is marked so that it can be copied later into main memory.
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write back
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write both
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write through
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write once
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Answer: A
6.In the memory hierarchy, the following memory has least capacity___________
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register
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primary memory
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cache
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Magnetic tape
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Answer: A
7.Replacing the block that has been not used for the longest period of time is ______________
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FIFO
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LRU
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MRU
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LFU
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Answer: B
8.In the following, which is efficient____________
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Programmed i/o
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Interrupt initiated i/o
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Direct memory access
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Memory mapped i/o
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Answer: C
9.In polling, the drawback is_________________
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cost is more
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complex hardware is required
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Time consuming
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Maintenance is more
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Answer: C
10.The number of basic I/O commands in IBM 370 computer IOP is _________________.
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50
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6
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8
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40
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Answer: A
11.A __________________ pipeline divides an arithmetic operation into sub operations for execution in the pipeline segments.
Answer: Arithmetic
12.____________________ must be performed to resolve multiple contention for the shared resources.
Answer: arbitration
13.To protect data from being changed simultaneously by 2 or more processors is called _____________-
Answer: mutual exclusion
14.The bus controller that monitors the cache coherence problem is referred as _________________
Answer: snoopy cache controller
15.___________________ processing deals with computations involving large matrices.
Answer: vector
16.The Dynamic RAM consists of _________________.
Answer: capacitors
17.The transfer of data between main memory and cache memory is __________________
Answer: block
18.The technique of segmentation suffers which fragmentation ______________________
Answer: external
19.The time taken to access a particular sector is _______________
Answer: latency time
20.The circuit which provides the interface between computer and similar interactive terminal is ________
Answer: UART